The present invention relates to a semiconductor integrated circuit device provided with a data output mechanism, and more specifically to a semiconductor integrated circuit device which uses a plurality of supply voltages so as to correspond to a microminiaturized structure.
In the semiconductor integrated circuit device, the elements thereof have now being microminiaturized rapidly with an increase in need for higher integration rate. Therefore, when an external supply voltage Vcc is applied as it is to the integrated circuits formed on a semiconductor substrate, there arise various problems in that a gate oxide film of the elements is broken down, hot carriers are produced, etc., so that the integrated circuits are deteriorated in reliability and durability. To overcome these problems, it has been required to provide an internal supply voltage deboosting circuit for reducing an external supply voltage within the semiconductor integrated circuit device itself. For instance, an external supply voltage of 5 V is deboosted down to about 3 V through the internal supply voltage deboosting circuit. When this deboosted supply voltage is used, it is also possible to reduce the power consumption of the semiconductor device.
For the reason as described above, although the internal supply voltage deboosting circuit has been adopted for the semiconductor device, so far it has been difficult to secure a margin in both the low voltage operation and the high voltage operation in the same integrated circuits. Therefore, when the supply voltage is low, since the transistor driving capability decreases, the conductances of the data outputting transistor and the internal voltage supply driving transistor have been both increased to supplement the decrease in the transistor driving capability and further to compensate for a delay in data output and a drop in the internally deboosted supply voltage. In contrast with this, when the supply voltage is high, since the transistor driving capability increases, the output noise increases. To overcome the above-mentioned problems, there has been proposed such an integrated circuit device that a switching circuit is additionally provided to increase the conductances of the data output transistor and the internal voltage supply driving transistor only in the low supply voltage operation, as compared with the high supply voltage operation.
FIG. 19 shows a circuit related to the invention which is provided with an internal voltage supply driving transistor for increasing the current supplying capability of the internal deboosting circuit when the external supply voltage is low. This circuit is composed of a P-channel transistor P12 having a source connected to an external supply voltage (Vcc) terminal and a gate connected to a control voltage generating circuit 1, a P-channel transistor P11 having a source connected to a drain of the P-channel transistor P12 and a gate connected to an internal deboosting control circuit 7, and a P-channel transistor P10 having a source connected to the external supply voltage (Vcc) terminal and a gate connected to the internal deboosting control circuit 7. In this circuit, an internal supply voltage Vint is outputted from the drains of the two P-channel transistors P10 and P11. In the drawing, the P-channel transistor P10 operates on the basis of a control signal .phi.D applied by the internal deboosting control circuit 7, without depending upon the external supply voltage. The P-channel transistor P12 is controlled on the basis of a control voltage .phi.A applied by the control voltage generating circuit 1 to the gate thereof, in such a way as to be operative only when the external supply voltage is lower than a predetermined voltage. Accordingly, the output circuit having the internal supply voltage driving transistor is composed of a full-voltage operating output section 5 provided with the transistor P10 and operative without depending upon the external supply voltage and a low-voltage operating output section 6 provided with the two transistors P11 and P12 and operative only when the external supply voltage is lower than a predetermined voltage.
FIG. 20 shows the dependency of the control voltage .phi.A upon the external supply voltage Vcc. FIG. 20 indicates that the control voltage .phi.A is kept roughly at zero volts in the low-voltage operation range. However, when the external supply voltage Vcc reaches a predetermined value, the control voltage .phi.A rises abruptly digitally. When the gate voltage of the driving P-channel transistor P12 is changed digitally as described above, since the internally deboosted potential also changes abruptly at the on-off switching point of the driving transistor, there exists a problem in that an erroneous operation occurs easily due to generation of supply voltage noise. Further, when the circuit is operated in the vicinity of the switched voltage, since the internal supply voltage Vint enters a discontinuous range, there exists a problem in that the circuit operation becomes unstable.
Further, in order to increase the conductance of the output transistor so that the data output speed increases when the external supply voltage is low, if the gate voltage of the output transistor is controlled so as to rise up to a predetermined value digitally as shown in FIG. 20, since the conductance of the output transistor changes abruptly in the vicinity of the voltage at which the output transistor is switched from on to off, the output noise cannot be reduced, with the result that an erroneous operation occurs. Further, since a discontinuous point is produced in the output transistor in the vicinity of the switched voltage, there exists a problem in that this exerts a harmful influence upon the dynamic characteristics of the circuit.
In addition, when the gate voltage of the driving transistor P12 is changed digitally, since the inspection process is complicated, the manufacturing cost thereof increases.
In more detail, FIG. 21 shows the change of the access time according to the external supply voltage Vcc. In the case of the device having no circuit for switching the conductance value of the data output transistor or the internal supply voltage driving transistor according to the external supply voltage Vcc, as shown by the dashed line L1, the access time increases with decreasing external supply voltage Vcc.
In the circuit related to the invention as shown in FIG. 19, since the P-channel transistor P12 is turned on in the vicinity of the external supply voltage Vcc of about 3.5 V for instance, the access time can be reduced sharply as shown in the dot-dashed line L2.
As far as the access time changes continuously as shown in the dashed line L1, there exists no problem as far as the circuit device is inspected by measuring the access times at only two points A and B. In the case of the circuit device in which the access time changes abruptly as shown by the dot-dashed line L2, however, it is necessary to measure the access time at a plurality of points C1, C2, C3, . . . (the access time changes abruptly at these points). This is because an erroneous operation may occur at or near the switched voltage due to the switching operation noise or due to the internal timing mismatch. Therefore, the inspection process is complicated and thereby a long inspection time is required.